1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to a method of fabricating a junction in which spacer profile is not distorted by subsequent processing such as screen oxide etch and pre-amorphization implant and anneal.
2) Description of the Prior Art
In sub-micron semiconductor technology, the use of self-aligned silicide processes have become widely accepted to minimize device series resistance and to tighten the design rule. Titanium silicide is the dominant material. The use of pre-amorphous implants for relieving stress-retarded reaction and increasing nucleation density is known.
However, the inventors have found that the integration of logic and memory on a single substrate has led to an increase in the quantity of etch steps after spacer formation. The inventors have found that these etch steps induce spacer deformation resulting in a triangular spacer profile and a loss of spacer width.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,731,239 (Wong et al.) shows an oxide layer over the STIduring the gate silicide process.
U.S. Pat. No. 5,451,546 (Grubisich et al.) shows a masking method for a salicide process to prevent damage to oxide spacers.
U.S. Pat. No. 5,384,285 (Sitaram et al.) teaches a salicide process with a selective wet etch using H2SO4+H2O2 or NH4OH+H2O2.
U.S. Pat. No. 5,605,854 (Yoo) shows a titanium silicide process integrated with a tungsten plug.
U.S. Pat. No. 5,668,024 (Tsai et al.) teaches a salicide process with dual spacers.
It is an object of the present invention to provide a method for fabricating a junction for a field effect transistor which does not cause distortion of the sidewall spacers.
It is another object of the present invention to provide a method for fabricating a junction for a field effect transistor which reduces source to drain leakage.
It is another object of the present invention to provide a method for fabricating a junction for a field effect transistor which reduces junction depletion.
It is another object of the present invention to provide a method for fabricating a junction for a field effect transistor which reduces the polymer on active regions and the polysilicon gate, while forming a pure titanium silicide.
It is yet another object of the present invention to provide a method for fabricating a junction for a field effect transistor which reduces source to drain leakage and junction depletion without forming multiple spacers on each sidewall of a gate.
To accomplish the above objectives, the present invention provides a method for fabricating a junction for a field effect transistor which does not cause distortion of the sidewall spacers during subsequent processing thereby reducing junction depletion and source to drain leakage. The invention uses a key selective etch for the etch of the resist protect oxide layer having a high selectivity between the silicon nitride spacer and the TEOS resist protect oxide layer. This etch does not significantly etch (or distort) the spacer.
The process begins by providing a substrate structure having a gate thereon. Sidewall spacers are formed on the sidewalls of the gate. Impurity ions are implanted into the substrate structure adjacent to the gate to form source and drain regions. A resist protect oxide layer is formed over the substrate structure. The resist protect oxide is patterned by forming a mask over the resist protect oxide layer having an opening over the gate and the source and drain regions. The resist protect oxide layer is selectively etched; thereby removing the resist protect oxide over the source and drain regions without distorting the sidewall spacers. A silicide region is formed on the source and drain regions using a salicide process comprising a pre-amorphous implant and one or more rapid thermal anneal steps.
The present invention provides considerable improvement over the prior art. The undistorted sidewall spacers reduce the distance that pre-amorphous implant damage extends under the gate during subsequent processing, which reduces the damage induced impurity ion diffusion under the gate. Because there is less impurity ion diffusion under the gate, junction depletion and source to drain leakage are reduced. Because the sidewall spacers are not distorted, additional spacers are not required to protect the substrate under the gate.
Since a typical dry etching process has more CHF3 gas than the etch of the present invention, this gas will react with the silicon in the active areas and on the polysilicon gate to form a polymer. This polymer impedes titanium silicide formation in these areas. The etch of the present invention reduces this problem by reducing the amount of CHF3 gas that these areas are exposed to.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.